TY  - BOOK
AU  - Palnitkar, Samir
AU  - Prabhu Goel
TI  - Verilog HDL
SN  - 9788177589184
U1  - 621.395 PAL-V 
CY  - Noida
PB  - Pearson
KW  - Hierarchical Modeling Concepts
KW  - Basic Concepts
KW  - Modules and Ports
ER  -